The NTE series Logic Level MOSFETs are compatible with the 5-volt power-supply requirement of logiccircuitry. These devices do not require an interface circuit between it and the CMOS logic driver; therefore, the extra cost of the interface circuit power supply is eliminated.
The chief physical structural difference between Logic Level and other MOSFETs, and the electrical reason for its difference in performance, is its gate insulation thickness, which has been reduced from 100nm industry standard to 50nm (500 angstroms), yet which retains the dynamic strength to handle the high voltage applied to power transistors. Since the surface inversion of the MOS channel is determined by the gate-insulator voltage field, the halving of the gate-oxide thickness should be expected to have a major effect on the gate voltage required. In fact, this reduction is the reason for voltage reduction from 10 volts (standard MOSFETs) to 5 volts (Logic Level MOSFETs).
Tight control of the temperature vs. time and oxygen vs. time profiles applied to the silicon substrate during oxide growth assures consistant preformance through the development of good transition regions between the oxide, the silicon below it, and thew polysilicon above it. The reduction in gate insulator thickness makes possible easy ON/OFF control of the Logic Level MOSFETs by CMOS logic alone, and by microprocessors.